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d a t a sh eet objective speci?cation supersedes data of 2003 apr 07 2003 dec 09 TDA8769 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling integrated circuits
2003 dec 09 2 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning 8 limiting values 9 thermal characteristics 10 characteristics 11 application information 11.1 output coding and control signals 11.2 TDA8769 in 3g radio receivers 11.3 application diagrams 11.4 demonstration board 11.5 definitions 11.5.1 static parameters 11.5.1.1 integral non-linearity (inl) 11.5.1.2 differential non-linearity (dnl) 11.5.2 dynamic parameters 11.5.2.1 signal-to-noise and distortion (sinad) 11.5.2.2 effective number of bits (enob) 11.5.2.3 total harmonic distortion (thd) 11.5.2.4 signal-to-noise ratio (snr) 11.5.2.5 spurious free dynamic range (sfdr) 11.5.2.6 intermodulation distortion (imd2 and imd3) 12 package outline 13 soldering 13.1 introduction to soldering surface mount packages 13.2 reflow soldering 13.3 wave soldering 13.4 manual soldering 13.5 suitability of surface mount ic packages for wave and reflow soldering methods 14 data sheet status 15 definitions 16 disclaimers
2003 dec 09 3 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 1 features 12-bit resolution optimized for both nyquist and high if sampling high-speed sampling rate up to 105 mhz maximum analog input frequency of 330 mhz (see application section) only 2 clock cycles latency 5 v power supplies and 3.3 v output power supply binary or twos-complement cmos outputs programmable complete conversion signal (ccs) cmos output in-range cmos compatible output cmos compatible static digital inputs lvttl and lvcmos compatible digital outputs differential clock input pecl; sine wave and ttl compatible integrated track-and-hold amplifier differential analog input external amplitude range control full-scale controllable from 1.5 to 1.9 v (p-p) voltage controlled regulator included temperature range from - 40 to +85 c. 2 applications cellular infrastructure (2.5g, 3g, etc.) base stations and zero-if or direct if sampling subsystems wireless and wired broadband communications wireless local loop (wll) local multipoint distribution service (lmds) advanced frequency modulation (fm) radio imaging (camera scanner and medical) cable modem or set top box radar and satellite hub systems. 3 general description the TDA8769 is a bicmos 12-bit analog-to-digital converter (adc) optimized for gsm/edge, w-cdma and cdma2000 radio transceivers, high data rate radios and other applications such as advanced fm radio and professional imaging. its main innovation is the rf sampling, based on a high-speed clock of up to 105 msps combined with high input frequencies of up to 250 mhz. it converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 105 mhz. the TDA8769 analog performances have been proven in various multi-carrier 3g radio receivers, providing the best-in-class adjacent channel selectivity (acs) up to 80 db. moreover the TDA8769 offers the lowest clock cycle latency, which enables competitive and optimized feedback loops in controlled systems. all static digital inputs (th, cen, otc, del0 and del1) are cmos compatible and all outputs are lvttl and lvcmos compatible. a sine wave clock input signal can also be used. 4 quick reference data tbf. 5 ordering information type number package sampling frequency (mhz) name description version TDA8769hw/6 htqfp48 plastic thermal enhanced thin quad ?at package; 48 leads; body 7 7 1.0 mm; heatsink sot545-2 60 TDA8769hw/8 80 TDA8769hw/10 105
2003 dec 09 4 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 6 block diagram handbook, full pagewidth mbl884 12 vref reference clock driver power management cmadc reference latch latch adc & amp fsref d0 to d11 v cco cen dec 13 11 47 46 42 1 16 38 35 20 5 19 23 to 34 22 ir otc del0 clkn 2 v cca1 3 v cca3 44 v cca4 40 v ccd1 17 v ccd2 vref inn in th cmadc TDA8769 track hold n.c. 6 to 10, 12, 14, 21, 45 agnd1 48 agnd3 4 agnd4 43 dgnd1 41 dgnd2 18 ognd 37 ccs 39 clk 15 del1 36 fig.1 block diagram. 7 pinning symbol pin type (1) description cmadc 1 o regulator output common mode adc output v cca1 2 p analog supply voltage 1 (5.0 v) v cca3 3 p analog supply voltage 3 (5.0 v) agnd3 4 g analog ground 3 dec 5 i/o decoupling node n.c. 6 - not connected n.c. 7 - not connected n.c. 8 - not connected n.c. 9 - not connected n.c. 10 - not connected vref 11 i reference voltage input n.c. 12 - not connected fsref 13 o reference output n.c. 14 - not connected del1 15 i complete conversion sampling delay input 1 del0 16 i complete conversion sampling delay input 0 v ccd2 17 p digital supply voltage 2 (5.0 v)
2003 dec 09 5 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 note 1. p = power supply, g = ground, i = input and o = output. dgnd2 18 g digital ground 2 otc 19 i control input twos complement output (active high) cen 20 i chip enable input (cmos level; active low) n.c. 21 - not connected ir 22 o in-range output d11 23 o data output bit 11 (msb) d10 24 o data output bit 10 d9 25 o data output bit 9 d8 26 o data output bit 8 d7 27 o data output bit 7 d6 28 o data output bit 6 d5 29 o data output bit 5 d4 30 o data output bit 4 d3 31 o data output bit 3 d2 32 o data output bit 2 d1 33 o data output bit 1 d0 34 o data output bit 0 (lsb) v cco 35 p supply voltage of data output (3.3 v) ccs 36 o complete conversion signal output ognd 37 g ground of data output clkn 38 i complementary clock input clk 39 i clock input v ccd1 40 p digital supply voltage 1 (5.0 v) dgnd1 41 g digital ground 1 th 42 i track-and-hold enable input (cmos level; active high) agnd4 43 g analog ground 4 v cca4 44 p analog supply voltage 4 (5.0 v) n.c. 45 - not connected in 46 i analog input voltage inn 47 i complementary analog input voltage agnd1 48 g analog ground 1 agnd5 exposed die pad g analog ground 5 symbol pin type (1) description
2003 dec 09 6 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 handbook, full pagewidth TDA8769hw mbl885 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 agnd1 inn in n.c. v cca4 agnd4 th dgnd1 v ccd1 clk clkn ognd fsref n.c. del1 del0 v ccd2 dgnd2 otc cen n.c. ir d11 d10 cmadc v cca1 v cca3 agnd3 dec n.c. n.c. n.c. n.c. n.c. vref n.c. ccs v cco d0 d1 d2 d3 d4 d5 d6 d7 d8 exposed die pad d9 fig.2 pin configuration. 8 limiting values tbf. 9 thermal characteristics symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air; (tbf) 25 k/w r th(c-a) thermal resistance from case to ambient in free air; (tbf) (tbf) k/w
2003 dec 09 7 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 10 characteristics v cca = 4.75 to 5.25 v; v ccd = 4.75 to 5.25 v; v cco = 2.7 to 3.6 v; agnd connected to dgnd; t amb = - 40 to +85 c; v in(p - p) - v inn(p - p) = 1.9 v - 0.5 dbfs; v vref =v cca3 - 1.75 v; v i(cm ) =v cca3 - 1.6 v; typical values measured at v cca =v ccd =5v, v cco = 3.0 v, t amb =25 c and c l = 10 pf; unless otherwise speci?ed. symbol parameter conditions test (1) min. typ. max. unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 2.7 3.0 3.6 v i cca analog supply current - 109 (tbf) ma i ccd digital supply current - 48 (tbf) ma i cco output supply current f clk = 80 msps; f i = 21.4 mhz - 17.5 (tbf) ma p tot total power dissipation f clk = 60 msps; f i = 21.4 mhz - 825 (tbf) mw f clk = 80 msps; f i = 21.4 mhz - 840 (tbf) mw f clk = 105 msps; f i = 21.4 mhz - 855 (tbf) mw clock inputs: pins clk and clkn; note 2 i nputs v il low-level input voltage referenced to dgnd; v ccd =5v pecl mode 3.19 - 3.52 v ttl mode dgnd - 0.8 v v ih high-level input voltage referenced to dgnd; v ccd =5v pecl mode 3.83 - 4.12 v ttl mode 2.0 - v ccd v i il low-level input current v clk or v clkn = 3.52 v (tbf) --m a v clk or v clkn = 0.80 v (tbf) -- ma i ih high-level input current v clk or v clkn = 3.83 v -- (tbf) m a v clk or v clkn = 2.00 v -- (tbf) ma d v clk differential ac input voltage for switching d v clk =v clk - v clkn ; ac mode; dc voltage level = 2.5 v (tbf) 1.5 (tbf) v r i input resistance f clk = 105 msps - (tbf) - m w c i input capacitance f clk = 105 msps - (tbf) - pf
2003 dec 09 8 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 t iming f clk(min) minimum clock frequency v th =v ccd -- 9 msps f clk(max) maximum clock frequency TDA8769hw/6 60 -- mhz/ msps maximum clock frequency TDA8769hw/8 80 -- mhz/ msps maximum clock frequency TDA8769hw/10 105 -- mhz/ msps t clkh clock high pulse width f i = 21.4 mhz (tbf) -- ns t clkl clock low pulse width f i = 21.4 mhz (tbf) -- ns analog inputs: pins in and inn i il low-level input current v vref =v cca3 - 1.75 v; v th = high - 10 -m a i ih high-level input current v vref =v cca3 - 1.75 v; v th = high - 10 -m a r i input resistance d - 8.4 - m w c i input capacitance d - 250 500 ff v i(cm) common mode input voltage v in =v inn ; output code = 2047 dv cca3 - 1.2 v cca3 - 1.6 v cca3 - 1.7 v digital inputs: pins otc, sh, del1, del0 and cen v il low-level input voltage dgnd - 0.3v ccd v v ih high-level input voltage 0.7v ccd - v ccd v i il low-level input current v il = 0.3v ccd (tbf) -m a i ih high-level input current v ih = 0.7v ccd -- (tbf) m a voltage controlled regulator output: pin cmadc v o(cm) common mode output voltage - v cca3 - 1.6 - v i l(cm) load current - 12ma symbol parameter conditions test (1) min. typ. max. unit
2003 dec 09 9 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 reference voltage input: pin vref; note 3 v ref(fs) full-scale ?xed voltage f i = 25 mhz; f clk = 105 msps - v cca3 - 1.75 - v v i(p-p) input voltage (peak-to-peak value) v i =v in - v inn ; v vref =v cca3 - 1.75 v; v i(cm) =v cca3 - 1.6 v - 1.9 - v i ref input current - 0.3 10 m a full-scale voltage controlled regulator output: pin fsref v o(fs) 1.9 v full-scale output voltage - v cca3 - 1.75 - v i l(fs) load current - 12ma digital outputs: pins d11 to d0 and ir o utput levels v ol low-level output voltage i ol = 2 ma dgnd - dgnd + 0.5 v v oh high-level output voltage i oh = - 0.4 ma v cco - 0.5 - v cco v i oz output current in 3-state output level between 0.5 v and v cco - 20 - +20 m a t iming ; see fig. 3 t d(s) sampling delay c l = 10 pf; note 4 - (tbf) (tbf) ns t h(o) output hold time c l = 10 pf (tbf) 3.7 - ns t d(o) output delay c l =10pf - 4.6 (tbf) ns 3- state output delay t dzh enable to high state - 2.8 - ns t dzl enable to low state - 7.5 - ns t dhz disable from high state - 7.2 - ns t dlz disable from low state - 2.9 - ns timing complete conversion signal: pin ccs t d(ccs) complete conversion signal delay c l = 10 pf; see table 4 and fig 4 del0 = low; del1 = high - 0 - ns del0 = high; del1 = low - 1.2 - ns del0 = high; del1 = high - 2.2 - ns symbol parameter conditions test (1) min. typ. max. unit
2003 dec 09 10 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 analog signal processing (50% clock duty factor) inl integral non-linearity f clk = 20 msps; f i = 400 khz - 1.7 (tbf) lsb dnl differential non-linearity f clk = 20 msps; f i = 400 khz; no missing code guaranteed - 0.4 (tbf) lsb e offset offset error v cca =v ccd =5v; v cco = 3.0 v; t amb =25 c; output code = 2047 -- 5 - mv e g gain error amplitude (spread from device to device) v cca =v ccd =5v; v cco = 3.0 v; t amb =25 c (tbf) - (tbf) %fs b analog bandwidth f clk = 105 msps; - 3 db; full-scale input; note 5 d - 330 - mhz thd total harmonic distortion TDA8769hw/6 b = nyquist; note 6 f i = 21.4 mhz -- 74 - dbc total harmonic distortion TDA8769hw8 b = nyquist; note 6 f i = 21.4 mhz -- 74 - dbc f i = 50 mhz -- 68 - dbc total harmonic distortion TDA8769hw/10 b = nyquist; note 6 f i = 21.4 mhz -- 67 - dbc f i = 78 mhz -- 63 - dbc n th(rms) thermal noise (rms value) shorted input; v th =v ccd ; f clk = 105 msps - (tbf) - lsb snr signal-to-noise ratio TDA8769hw/6 f i = 21.4 mhz; note 7 b = nyquist - 66 - dbc signal-to-noise ratio TDA8769hw/8 f i = 21.4 mhz; note 7 b = nyquist - 66 - dbc f i = 50 mhz; note 7 b = nyquist - 66 - dbc b = 5 mhz - 72.4 - dbc signal-to-noise ratio TDA8769hw/10 f i = 21.4 mhz; note 7 b = nyquist - 64 - dbc f i = 78 mhz; note 7 b = nyquist - 62 - dbc b = 5 mhz - 72 - dbc symbol parameter conditions test (1) min. typ. max. unit
2003 dec 09 11 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 notes 1. explanation tests: a) d = guaranteed by design b) c = guaranteed by characterization c) i = industrially tested for 100%. sfdr spurious free dynamic range TDA8769hw/6 f i = 21.4 mhz b = nyquist - 77 - dbc spurious free dynamic range TDA8769hw/8 f i = 21.4 mhz b = nyquist - 77 - dbc f i = 50 mhz b = nyquist - 70 - dbc b = 5 mhz - 80.8 - dbc spurious free dynamic range TDA8769hw/10 f i = 21.4 mhz b = nyquist - 68 - dbc f i = 78 mhz b = nyquist - 67 - dbc b = 5 mhz - 84 - dbc enob effective number of bits TDA8769hw/6 f i = 21.4 mhz; note 8 b = nyquist - 10.6 - bit effective number of bits TDA8769hw/8 f i = 21.4 mhz; note 8 b = nyquist - 10.6 - bit f i = 50 mhz; note 8 b = nyquist - 10.3 - bit b = 5 mhz - 11.7 - bit effective number of bits TDA8769hw/10 f i = 21.4 mhz; note 8 b = nyquist - 10 - bit f i = 78 mhz; note 8 b = nyquist - 9.6 - bit b = 5 mhz - 11.8 - bit im2 second order intermodulation distortion f i 1 = 15 mhz and f i 2 = 18 mhz; note 10 f clk = 80 msps - (tbf) - dbfs im3 third order intermodulation distortion f i 1 = 15 mhz and f i 2 = 18 mhz; note 10 f clk = 80 msps - 82 - dbfs ber bit error rate f i = 25 mhz; v in = 16lsb at code 2047; f clk = 105 msps - (tbf) - symbol parameter conditions test (1) min. typ. max. unit
2003 dec 09 12 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 2. the circuit has two clock inputs: clk and clkn. there are 5 modes of operation: a) pecl mode 1: (dc level varies proportionally with v ccd ) clk and clkn inputs are at differential pecl levels. b) pecl mode 2: (dc level varies proportionally with v ccd ) clk input is at pecl level and sampling is taken on the falling edge of the clock input signal. a dc level of 3.65 v has to be applied on clkn decoupled to gnd via a 100 nf capacitor. c) pecl mode 3: (dc level varies proportionally with v ccd ) clkn input is at pecl level and sampling is taken on the rising edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. d) differential ac driving mode 4: when driving the clk input directly and with any ac signal of minimum 1 v (p-p) and with a dc level of 2.5 v, the sampling takes place at the falling edge of the clock signal. when driving the clkn input with the same signal, sampling takes place at the rising edge of the clock signal. it is recommended to decouple the clkn or clk input to dgnd via a 100 nf capacitor. e) ttl mode 5: clk input is at ttl level and sampling is taken on the falling edge of the clock input signal. in that case clkn pin has to be connected to the ground. 3. the adc input range can be adjusted with an external reference connected to pin vref. this voltage has to be referenced to v cca . 4. output data acquisition: the output data is available after the maximum delay of t d(s) . 5. the - 3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input being a full-scale sine wave. 6. the total harmonic distortion is obtained with the addition of the first five harmonics. 7. the signal-to-noise ratio takes into account all harmonics above five and noise up to nyquist frequency. 8. the effective number of bits, or enob, are obtained via a fast fourier transform (fft). the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise and distortion, or sinad, is given by sinad = enob 6.02 + 1.76 db. 9. intermodulation measured relative to either tone with analog input frequencies of (tbf) and (tbf) mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full-scale input to the converter ( - 6 db below full-scale for each input signal). 10. im2 is the ratio of the rms value of either input tone to the rms value of the worst case second order intermodulation product. im3 is the ratio of the rms value of either input tone to the rms value of the worst case third order intermodulation product.
2003 dec 09 13 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 handbook, full pagewidth vi ckp 0.5 v n d0 to d11 v cco - 0.5 v 50% data n - 1 data n data n + 1 t d(o) t ds(i) t h(o) mdb034 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 fig.3 output timing diagram. handbook, full pagewidth mbl874 d0 to d11 ccs t d(ccs) fig.4 complete conversion signal timing diagram.
2003 dec 09 14 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 11 application information 11.1 output coding and control signals table 1 output coding with differential inputs (typical values to agnd); v in(p - p) - v inn(p - p) = 1.9 v - 0.5 dbfs; v vref =v cca3 - 1.75 v table 2 mode selection table 3 track-and-hold selection table 4 complete conversion signal selection 11.2 TDA8769 in 3g radio receivers TDA8769 has been proven in many 3g receivers with various operating conditions regarding input frequency, signal input frequency bandwidth and sampling frequency. TDA8769 provides a maximum analog input frequency of 250 mhz. it allows a significant cost reduction of the rf front-end, from two mixers to only one, even in multicarrier architecture. table 5 shows possible applications with the TDA8769 in high if sampling mode. code v in(p-p) v inn(p-p) ir binary outputs (d11 to d0) twos complement outputs (d11 to d0) under?ow <2.925 >3.875 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2.925 3.875 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 -- 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 ::: : : 2047 3.4 3.4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ::: : : 4094 -- 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 4095 3.875 2.925 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 over?ow >3.875 <2.925 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 control input twos complement output (otc) chip enable not (cen) output data (d0 to d11 and ir) 0 0 binary; active 1 0 twos complement; active dont care 1 high impedance control input track-and-hold (th) mode 1 active 0 inactive; tracking del1 del0 output signal 0 0 inactive 0 1 active (for timing values, see chapter 10) 10 11
2003 dec 09 15 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 table 5 examples of possible f i , f clk and f i bandwidth combinations supported for a dual carrier w_cdma receiver, the most important parameters are the sensitivity and adjacent channel selectivity (acs). in w-cdma, it can be far below the noise floor, is defined by the sensitivity to noise ratio (senr). its value is negative due to the gain processing. the adjacent channel power ratio (acpr) is the difference between the peak and noise floor. it represents the ratio of the adjacent channel power and the average power of the channel. the acs is defined by the sum of senr and acpr. figure 5 illustrates the relation between these parameters. on a typical application with the TDA8769 device, the acs obtained is 80 db with an acpr of 70 db and a senr of 10 db. moreover, the noise figure (nf) of the TDA8769 is 31.5 db. f i (mhz) f clk (mhz) f i bw (mhz) snr (db) sfdr (dbc) 250 9.60 0.20 66.5 79.9 243.95 9.60 0.20 62.6 68.5 243.95 19.20 0.20 68.4 77.2 243.95 52.00 0.20 65.7 80.0 190 40.00 1.25 72.0 80.0 106 76.80 5.00 70.8 83.6 86 76.80 5.00 72.2 87.1 80 61.44 10.00 (tbf) (tbf) 70 40.00 5.00 70 70 69.99 58.98 1.25 (tbf) (tbf) 27 51.2 3.5 (tbf) (tbf) 10.8 32.5 0.30 84.3 83.0 handbook, full pagewidth mbl875 acpr nf interfering channel wanted channel acs noise floor sensitivity thermal noise senr fig.5 adjacent channel selectivity and analog-to-digital converter sensitivity.
2003 dec 09 16 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 11.3 application diagrams mdb035 q q d ttl 270 w 270 w 50 w TDA8769 clkn clk fig.6 ttl to pecl translator application. mdb036 TDA8769 clkn clk ttl fig.7 ttl single-ended clock application.
2003 dec 09 17 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 fig.8 application diagram. tbf
2003 dec 09 18 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 11.4 demonstration board handbook, full pagewidth mbl876 2 1 3 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a19 a18 a20 a21 a22 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b19 b18 b20 b21 b22 j1 36 TDA8769hw 35 ccs v cco 34 d0 33 d1 32 d2 31 d3 30 d4 29 d5 28 d6 27 d7 26 d8 25 d9 37 ognd 38 clkn 39 clk 40 v ccd1 41 dgnd1 42 th 43 agnd4 44 v cca4 45 n.c. 46 in 47 inn 48 agnd1 4 agnd3 5 dec 6 n.c. 7 n.c. 8 n.c. 9 n.c. 10 n.c. 11 vref 12 n.c. 24 23 22 21 20 19 18 17 16 15 14 13 d10 d11 ir n.c. cen otc dgnd2 v ccd2 del0 del1 n.c. fsref ic1 v cca (44) c2 330 nf c3 100 nf fl1 470d_0d0_s c18 10 nf (2/3) c19 10 nf v ccd1 (40) c13 330 nf c15 100 nf fl3 470d_0d0_s c17 10 nf v ccd2 (17) c11 330 nf c6 100 nf fl2 470d_0d0_s fl4 hf70a08s c20 10 nf tm2 tm3 out out adj in 32 1 v cco (35) c10 1 m f c16 10 nf lm317d2t gnd in 13 2 mc7805d2t r8 r7 330 w 240 w r6 750 w tm1 c9 470 nf d2 pwr lgt679_c0 c8 4.7 m f 16 v c7 22 m f 20 v d1 byd17g j5 1 12 v j5 2 gnd mstba2.5_20_5d8 ic3 ic2 d0 css pcn12a_44p_2.54ds s4 v ccd2 on del1 s8 v ccd2 on del0 v ccd2 s6 1k2 v ccd2 on otc s7 1k2 v ccd2 off cen r125680 j3 trig r9 50 w v cco c12 10 nf v cc gnd 2 3 5 4 ic4 r10 150 w v cco ir d3 ls6t670 r11 150 w 1 4 2 3 74ahc1guo4gw r125680 j2 r2 50 w v ccd1 on 1k2 th s1 v cca s3 ext 1k2 v cca r4 2.4 k w p2 1 k w r5 1.2 k w c5 100 nf c1 220 nf v cca v cca 1 2 cmadc v cca1 3 vcca3 c4 100 nf v cca tb2 s2 ext 1k2 v cca p1 5 k w cmadc c14 330 nf tb1 v cca r3 100 w r1 100 w tr1 t1_6t_kk81 in r125680 j1 clk 4 6 5 50 w agnd agnd agnd agnd agnd dgnd v ccd1 dgnd dgnd dgnd agnd agnd agnd dgnd v cco agnd dgnd agnd agnd agnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd tp1 dgnd dgnd dgnd dgnd agnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd agnd agnd agnd fig.9 demonstration board schematic.
2003 dec 09 19 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 mbl877 r2 tm2 c1 j1 s1 s2 p1 1tb1 r1 tr1 ic1 r3 c3 c2 fl1 ic2 j5 21 d1 c7 tm3 j3 tm1 r5 d2 r6 c8 ic3 c10 tp1 c11 c12 r11 r10 p2 r7 r8 c9 c5 r4 d3 fl2 s3 s4 s5 s6 s7 r9 tb2 j4 j2 c4 c5 1 fig.10 component placement, top view. mbl878 ic4 c20 fl3 c13 c15 fl4 c18 c14 c19 c17 c16 fig.11 component placement, bottom view.
2003 dec 09 20 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 mbl879 fig.12 printed-circuit board tracks, layout 1. mbl880 fig.13 printed-circuit board tracks, layout 2. mbl881 fig.14 printed-circuit board tracks, layout 3.
2003 dec 09 21 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 11.5 de?nitions 11.5.1 s tatic parameters 11.5.1.1 integral non-linearity (inl) inl is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). the inl of code i is obtained from the following equation: where: i = code value v in = input voltage for code i s = slope of the ideal straight line (code width). 11.5.1.2 differential non-linearity (dnl) dnl is the deviation in code width from the value of one lsb. the dnl of code i is obtained from the following equation: where: i=0to2 n - 2 v in = input voltage for code i s = slope of the ideal straight line. 11.5.2 d ynamic parameters figure 15 shows the spectrum of a single tone full-scale input sine wave with frequency f t , conforming to coherent sampling and digitized by the adc under test. coherent sampling means that , where m is the number of cycles, n the number of samples and both m and n being a relative prime. remark: the parameter p noise used in the following equations includes the power of the random noise, non-linearities, sampling time errors and quantization noise. inl i () v in i () v in ideal () C s ---------------------------------------------- = dnl i () v in i1 + () v in i () C s -------------------------------------------- - = f t f s --- - m n ---- - = handbook, full pagewidth mbl882 0 0 measured output range (mhz) 2.5 magnitude - 20 - 40 - 60 - 80 - 100 - 120 - 160 5 7.5 10 12.5 15 17.5 20 22.5 25 27 - 140 imd3 fig.15 spectrum of a full-scale input sine wave with frequency f t .
2003 dec 09 22 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 11.5.2.1 signal-to-noise and distortion (sinad) sinad is the ratio of the signal power to the noise plus distortion power, excluding the dc component, at a given sample rate and input frequency: db. 11.5.2.2 effective number of bits (enob) enob is derived from sinad and gives the theoretical resolution an ideal adc would require to obtain the same sinad measured on the actual adc. a good approximation is: 11.5.2.3 total harmonic distortion (thd) thd is the ratio of the power of the harmonics to the power of the signal frequency. the equation for k - 1 harmonics is: db where: as usual the value of k = 6 (i.e. the calculation of thd is done with the first 5 harmonics). 11.5.2.4 signal-to-noise ratio (snr) snr is the ratio of the signal power to the noise power, excluding the harmonics and dc component of the signal: db 11.5.2.5 spurious free dynamic range (sfdr) the sfdr specifies the available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious signal, harmonic and non-harmonic, excluding the dc component. db 11.5.2.6 intermodulation distortion (imd2 and imd3) figure 16 shows the spectral analysis of a dual tone sine wave input, at frequencies f t1 and f t2 , meeting the coherence criterion. the 2nd and 3rd order intermodulation distortion products, imd2 and imd3 respectively, are defined with a dual tone input. imd2 is defined as the ratio of the rms value of either tone to the rms value of the second order intermodulation product, imd3 with the third order intermodulation product. the imd is given by: db sinad 10log 10 p signal p noise + distortion ------------------------------------- - ? ?? = enob sinad 1.76 C 6.02 ------------------------------------- = thd 10log 10 p harmonics p signal ------------------------ - ? ?? = p harmonics a 2 2 a 3 2 ... a k 2 +++ = p signal a 1 2 = snr 10log 10 p signal p noise --------------- - ? ?? = sfdr 10log 10 a 1 max s () -------------------- ? ?? = imd 10log 10 p intermod p signal --------------------- ? ?? =
2003 dec 09 23 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 where: . is the power of the intermodulation component at f t . p intermod a 2 im ft1 ft2 C () a 2 im ft1 ft2 + () C a 2 im ft1 2ft2 C () a 2 im ft1 2ft2 + () ? a 2 im 2ft1 ft2 C () a 2 im f2t1 ft2 + () +++++ = p signal a 2 ft1 a 2 ft2 + = a 2 im ft () handbook, full pagewidth mbl883 measured output range (mhz) magnitude sfdr a 2 a 3 a k a 1 fig.16 spectral analysis with dual tone.
2003 dec 09 24 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 12 package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 0.5 9.1 8.9 0.89 0.61 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot545-2 99-08-04 03-04-07 d (1) e (1) 7.1 6.9 9.1 8.9 d h e h 4.6 4.4 4.6 4.4 0.89 0.61 b p e q e a 1 a l p detail x l b 12 1 48 37 d h b p e h a 2 v m b d z d a c z e e v m a x 25 36 24 13 y pin 1 index w m w m 0 2.5 5 mm scale htqfp48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad sot545-2 d h e h exposed die pad side (a ) 3
2003 dec 09 25 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 13 soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 13.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson-t and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 dec 09 26 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 13.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on flex foil. however, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. the appropriate soldering profile can be provided on request. 9. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, htsson..t (3) , lbga, lfbga, sqfp, ssop..t (3) , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable cwqccn..l (8) , pmfp (9) , wqccn..l (8) not suitable not suitable
2003 dec 09 27 philips semiconductors objective speci?cation 12-bit, 60/80/105 msps analog-to-digital converter (adc) nyquist/high if sampling TDA8769 14 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 15 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r78/02/pp 28 date of release: 2003 dec 09 document order number: 9397 750 11706

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